Design & Reuse
Catalog of SIP Cores
System on Chip design resources
155 IP
151
0.0
Prism Video Encoder IP – E400 Series
The Pulsar D400 Series Decoder IP is Allegro DVT’s next-generation, multi-format, multi-stream hardware Decoder, designed to deliver high-performance,...
152
0.0
RTP packetizer IP-cores for JPEG XS compressed video encapsulation over ST2110-22
The IPX-RTP-XS IP-cores enable the RTP packetization/depacketization and are designed to be used with intoPIX video codecs. The IP-cores can directly ...
153
0.0
Multi-Channel HDTV H.264/AVC Limited Baseline Video Decoder
The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm. The core decodes a bitstream produced by the OLH2...
154
0.0
Multi-Channel MJPEG Decoder
The logiJPGD Multi-Channel Motion JPEG Decoder is JPEG standard Baseline DCT compliant decoder IP core for still image and video decompression applica...
155
0.0
AVC Intra Encoder & Decoder
The H.264 Intra Frame Codec Core is a high performance & highly optimized video compression- decompression engine targeted primarily at FPGAs. It is c...